A methodology to evaluate the Holding Time in CMOS Logic Gates with Stuck-Open Fault

This work proposes a methodology to measure the holding time in nanometer technologies. In nanotechnologies, the behavior of Stuck-Open Fault (SOF) is more affected by the high leakage currents and low signal node capacitance. Therefore, evaluate the holding time is very important because depending on the operation frequency that the circuit is analyzed, some pair of vectors cannot be used to detect a SOF. The main objective of the proposed method is capture the real time when the output switches due to the interaction between leakage currents and stuck open transistor. The correct values of holding time guarantee good test performance and avoid that some faults be electrically masked.